With recent advances in the development of high density very large scale integration (VLSI) circuits, the dimensions of the devices continue to shrink resulting in a corresponding decrease in the gate oxide thicknesses in the CMOS devices. This decrease, relative to breakdown voltage, has resulted in the greater susceptibility of these devices to damage from the application of excessive voltages such as caused by an electrostatic discharge (ESD) event. During an ESD event, charge is transferred between one or more pins of the integrated circuits and another conducting object in a short period of time, typically less than one microsecond. The charge transfer generates voltages that are large enough to break down insulating films, e.g., gate oxides on MOSFET devices, or that can dissipate sufficient energy to cause electrothermal failures in the devices. Such failures include contact spiking, silicon melting, or metal interconnect melting. Consequently, in order to deal with transient ESD pulses, an integrated circuit must incorporate protection circuits at every input and I/O pin. Various circuit structures for ESD protection can be found, e.g., in U.S. Pat. Nos. 5,019,888 to Scott et al; 5,182,220 to Ker et al; 5,218,222 to Roberts; and 5,329,143 to Chan; and in the literature in "Internal Chip ESD Phenomena Beyond the Protection Circuit", C. Duvvury, IEEE Transactions on Electron Devices, Vol.35, No.12, December 1988; "A Low-Voltage Triggering SCR for On-Chip ESD Protection at Output and Input Pads", A. Chatterjee, IEEE Electron Device Letters, Vol.12, No.1, January 1991; and "ESD Protection in a Mixed Voltage Interface and Multi-Rail Disconnected Power Grid Environment in 0.50- and 0.25-.mu.m Channel Length CMOS Technologies", S. Voldman, EOS/ESD Symposium Proceedings, pp. 125-134, 1994.
An example of one form of ESD protection device of the general type such as discussed in the above-cited U.S. Pat. No. 5,329,143 to T. C. CHAN ET AL, is shown in FIG. 1 in cross-section embodying a known low-voltage integrated circuit (IC) device 10, in the form of a MOSFET gate with PMOS and NMOS transistors 2 and 4 indicated schematically in FIG. 1A. Device 10 is fabricated from a semiconductor substrate 12 of a first conductivity type, such as P+ conductivity, with various diffusions and circuit components formed thereon to provide protection against ESD damage due to excessive stresses. Included is the thin-oxide NMOS transistor or N-channel device 4, composed of N+ regions, 18 and 20, having a gate electrode 22 with a thin oxide 24 therebetween, and disposed in a P-well region 26. The outer N+ region 20 of MOSFET 4 is connected to a contact 28, that may be coupled to a voltage source, an I/O pad, or the IC internal circuits, and the inner N+ region 18 is coupled to an adjacent outer P+ conductivity region 14 by a contact or bus 16 which is connected to a negative voltage source VSS or ground. The NMOS thick-field device 4 deals with either positive or negative ESD stresses developed between the Vss voltage on contact 16 and the voltage communicated from the contact 28. The N+ diffusion regions, 18 and 20, and underlying P-well 12 act as a bipolar device when there is an excessive positive stress on the contact 28 with respect to Vss, i.e., a parasitic lateral NPN transistor results, with its base at the P-well 12, its emitter at N+ region 18, and its collector or drain at N+ region 20. Punch through occurs at the NP junction (20,12), the drain breaks down, typically at about 13 volts, and current flows from contact 28 to ground through the N+ regions 20 and 18, to offer protection to the other circuit devices. Particularly, upon punch through the generated electrons are swept into the collector region 20. The generated holes injected into the base region 12 cause the substrate voltage to increase, forward biasing the emitter junction, and causing the NPN transistor to turn ON. As a consequence, injection of electrons from the emitter 18 into the base 12 is increased and those electrons reaching the collector-base junction (20,12) generate new electron hole pairs and current growth continues. This "positive feedback" would cause the emitter-to-collector current to increase indefinitely, resulting in damage to the device if the current is not somehow limited. Also, when a negative stress on the contact 28 with respect to Vss occurs, a forward biased diode would result between P+ region 14 and N+ region 20, through the P-well 12, that would turn ON to protect the other internal integrated devices.
A typical IC chip has a plurality of parallel NMOS devices formed therein as shown in FIG. 2. The chip layout shown has a 100 .mu.m wide N+ source region on the left side and a 100 .mu.m wide N+ drain region on the right side with a 0.85 .mu.m polysilicon gate above and between them and a P+ substrate disposed 9 .mu.m therefrom. An equivalent circuit schematic is seen in FIG. 3 showing the array of parallel NMOS devices T1, T2, T3, T4, . . . etc., and their respective base currents Ib1, Ib2, Ib3, Ib4 . . . etc., and drain currents Ic1, Ic2, Ic3, Ic4 . . . etc. The resistance Rsub between the substrate and T1, and the successive resistances between the successive devices (.DELTA.R) are indicated as R1, R2, R3, R4 . . . etc. The relationships among these parameters are as follows: R1&lt;R2&lt;R3&lt;R4 . . . etc.; Ic1&gt;Ic2&gt;Ic3&gt;Ic4 . . . etc.; and Ib1&gt;Ib2&gt;Ib3&gt;Ib4 . . . etc. A problem with this arrangement, however, is that the ESD pass voltage is effected by different processes due to current crowding and the uniformity of the current distribution is effected. It is therefore desirable to be able to reduce the current crowding and produce a uniform current distribution as much as possible.
It is accordingly an object of the present invention to provide an enhanced ESD protection performance apparatus and method for protecting VLSI circuits and particularly parallel NMOS devices.
It is another object of the invention to provide an enhanced ESD protection performance apparatus and method for protecting VLSI circuits and particularly parallel NMOS devices that reduces current crowding and produces a more uniform current distribution.
It is further object of the invention to provide an enhanced ESD protection performance apparatus and method for protecting VLSI circuits and particularly parallel NMOS devices by utilizing an additional P-well implantation to reduce the P-well resistivity to produce a more uniform current distribution.